1. Field of the Invention
The present invention relates to field effect transistors and bipolar transistors. More particularly the present invention relates to a device which combines the desirable features of both field effect transistors and bipolar transistors.
2. Description of the Prior Art
Si bipolar transistors and CMOS devices have been combined in integrated circuits (BiCMOS). This is discussed in an article entitled "Advanced BiCMOS Technology for High Speed VLSI", Ikeda T. et al., IEDM Conference Proceeding p. 408, 1986. The combination is motivated by a need to increase the speed of CMOS devices while reducing the power dissipation of Si bipolar devices for digital applications. Heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HEMTs, HISHEMTs), based on III-V semiconducting compounds such as AlGaAs/GaAs and InP/InGaAs and AlInAs/InGaAs perform better than Si bipolar transistors and CMOS at high frequencies. This is discussed in articles entitled "High-Gain Al.sub.0.48 In.sub.0.5 As/Ga.sub.0.53 As Vertical n-p-n Heterojunction Bipolar Transistors Grown by Molecular-Beam Epitaxy", Malik, R. J. et al., IEEE Electron Device Letters, EDL-4, 383, 1983 and "Self-Aligned AlGaAs/GaAs Heterojunction Bipolar Transistors with Improved High-Speed Performance", Chang et al., IEEE Device Research Conference, Santa Barbara, Calif., 1987. A bipolar transistor has a higher current gain and higher transconductance than a field-effect transistor, but its input impedance is much lower than that of the FET. A high current gain and transconductance results in superior high frequency performance. On the other hand, a high input impedance results in lower noise devices that are cascadable in multistage amplifiers. Therefore, a combination of HBTs and FETs in such a way as to take advantage of the best feature of both is desirable, but has not been proposed.
U.S. Pat. No. 4,214,215 by Mellen, A. J. and Reitlinger, A. discloses a low noise-high gain JFET amplifier for a piezoelectric transducer. A conventional transistor or Darlington pair is provided with a base electrode coupled to the source electrode of the JFET and a collector electrode coupled to the JFET drain electrode. The emitter circuit of the transistor includes a first voltage divider for feeding back a portion of the emitter signal to the base circuit of the transistor. A second voltage divider is provided in the feedback path from the first divider to the transistor base to apply a portion of the base feedback signal to the JFET gate through the gate input resistor.
U.S. Pat. No. 4,216,393 by Gillberg, J. E. and Kucharewski, N. discloses a drive circuit for controlling current output rise and fall times. This drive circuit has output current passing through at least one bipolar transistor. The rise and fall times of the output current are predetermined by controlling the rate of current change in the master path of a current mirror amplifier which has a separate slave path connected to supply base current for each bipolar transistor.
U.S. Pat. No. 4,241,314 by Iwamatsu, M. discloses a transistor amplifier circuit of the type wherein two pairs of circuits are used each including a source follower type field effect transistor in the input stage and a bipolar type transistor in the succeeding stage and wherein the paired bipolar transistors constitute a differential amplifier. A plurality of constant current sources are connected so that the sum of the currents flowing through respective transistors will be constant for the purpose of driving the field effect transistors with small voltage in an active region.
U.S. Pat. No. 4,253,033 by Redfren, T. P. discloses a wide bandwidith CMOS class A amplifier. In this circuit a CMOS inverter is coupled to drive a bipolar transistor emitter follower which has a field effect transistor load. The load transistor is provided with a d.c. bias that causes the circuit to function as a class A amplifier. The amplifier has a gain-band-width product that is much higher than can be achieved with CMOS invertors alone and such amplifiers can be cascaded to achieve extremely high gain values.
U.S. Pat. No. 4,492,932 by Rusznyak, A. discloses an amplifier circuit having a high impedance input and a low impedance output. This circuit includes an input field effect transistor connected in a source-follower configuration, a bipolar transistor connected in an emitter-follower configuration and controlled by the transistor, a current source serving as a load for the transistor, an amplifier being controlled by the transistor and a resistor which serves as a load for the transistor and which connects the source of the transistor to the output of the amplifier. This output also serves as the output of the circuit which is supplied by a voltage source applied between the current source and the collector of the transistor. The d.c. voltage drop in the resistor is low which permits the circuit to be supplied at a low voltage and to dissipate a small amount of energy.
The patents listed above are related to the present invention, however, the above designs will not work at high frequencies. The patents above that describe the method of fabrication disclose that the circuits will be implemented with only low frequency silicon-based devices. The present invention, however, overcomes the low frequency limitation and other deficiencies by providing a field effect transistor-heterojunction bipolar transistor pair that operates at high frequencies.